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  • Addressing modes of microprocessor 8085



The way of specifying data to be operated by an instruction is called addressing
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:

  1. Immediate Addressing Mode –
    In immediate addressing mode the source operand is always data. If the data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
    Examples:
    MVI B 45 (move the data 45H immediately to register B)
    LXI H 3050 (load the H-L pair with the operand 3050H immediately)
    JMP address (jump to the operand address immediately).


  1. Register Addressing Mode –
    In register addressing mode, the data to be operated is available inside the register(s) and register(s) is(are) operands. Therefore the operation is performed within various registers of the microprocessor.
    Examples:
    MOV A, B (move the contents of register B to register A)
    ADD B (add contents of registers A and B and store the result in register A)
    INR A (increment the contents of register A by one)
  2. Direct Addressing Mode –
    In direct addressing mode, the data to be operated is available inside a memory location and that memory location is directly specified as an operand. The operand is directly available in the instruction itself.
    Examples:
    LDA 2050 (load the contents of memory location into accumulator A)
    LHLD address (load contents of 16-bit memory location into H-L register pair)
    IN 35 (read the data from port whose address is 01)
  3. Register Indirect Addressing Mode –
    IN register indirect addressing mode, the data to be operated is available inside a memory location and that memory location is indirectly specified b a register pair.
    Examples:
    MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator)
    LDAX B (move contains of B-C register to the accumulator)
    LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
  4. Implied/Implicit Addressing Mode –
    In implied/implicit addressing mode the operand is hidden and the data to be operated is available in the instruction itself.
    Examples:
    CMA (finds and stores the 1’s complement of the contains of accumultor A in A)
    RRC (rotate accumulator A right by one bit)
    RLC (rotate accumulator A left by one bit)

Interrupts in 8085

Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
  • Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
  • Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR.
  • Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5.
  • Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP.
  • Software interrupt − In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
  • Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting source is called an ISR.

TRAP

It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers the control to the location 0024H.

RST7.5

It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH address.

RST 6.5

It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H address.

RST 5.5

It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH address.

INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
  • The microprocessor checks the status of INTR signal during the execution of each instruction.
  • When the INTR signal is high, then the microprocessor completes its current instruction and sends active low interrupt acknowledge signal.
  • When instructions are received, then the microprocessor saves the address of the next instruction on stack and executes the received instruction.

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